LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 306

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

DIF bit
differential mode
DIFFSENS SCSI signal
disable halt on parity error or ATN
disable single initiator response bit
DMA byte counter register
DMA command register
DMA control register
DMA core
DMA direction bit
DMA FIFO bits
DMA FIFO empty bit
DMA FIFO register
DMA FIFO size bit
DMA interrupt enable register
DMA interrupt pending bit
DMA mode register
DMA next address register
DMA SCRIPTS pointer register
DMA SCRIPTS pointer save register
DMA status register
DMODE register
DNAD register
DSA register
DSP register
DSPS register
DSTAT register
E
enable parity checking bit
enable read line bit
enable read multiple bit
enable response to reselection bit
enable response to selection bit
enable wide SCSI bit
encoded chip SCSI ID
encoded destination SCSI ID bit
encoded destination SCSI ID bits
extend SREQ/SACK filtering bit
external memory interface
extra clock cycle of data setup bit
F
fetch enable
fetch pin mode bit
FIFO byte control bits
FIFO flags bits
flush DMA FIFO bit
FMT
function complete bit
IX-2
DIFFSENS
direction control pins
operation
SCSI differential mode bit
configuration
flash ROM updates
GPIO4 bit
multiple byte accesses
slow memory
system requirements
5-34
5-73
2-2
5-63
5-31
5-46
2-20
5-19
5-46
5-45
4-19
5-27
5-43
5-23
5-47
2-7
2-8
5-42
5-38
5-42
5-39
,
5-49
5-47
5-37
5-23
5-51
5-23
5-54
5-12
5-30
5-41
5-14
2-6
7-3
5-49
5-45
4-16
2-6
,
5-34
5-5
2-6
5-44
7-13
5-45
5-57
Index
,
5-73
5-50
5-46
2-7
5-74
5-14
5-22
5-18
5-14
5-6
5-7
5-76
5-46
G
general purpose pin control register
general purpose register
general purpose timer expired bit
general purpose timer period bits
general purpose timer scale factor bit
GPCNTL register
GPIO enable bit
GPIO[4:0] bits
GPREG register
H
halt SCSI clock bit
handshake-to-handshake timer bus activity enable bit
handshake-to-handshake timer expired bit
handshake-to-handshake timer period bit
high impedance mode bit
I
I/O instructions
illegal instruction detected bit
immediate arbitration bit
input
instruction prefetching
instructions
internal RAM, see also SCRIPTS RAM
interrupt status register
interrupt-on-the-fly bit
interrupts
IRQ disable bit
IRQ mode bit
ISTAT register
J
JTAG support
L
last disconnect bit
latched SCSI parity bit
latched SCSI parity for SD[15:8] bit
load and store instructions
lost arbitration bit
LSI53C700 family compatibility bit
prefetch enable bit
prefetch flush bit
prefetch unit flushing
block move
I/O
load and store
memory move
read/write
transfer control
fatal vs. nonfatal interrupts
halting
IRQ disable bit
masking
sample interrupt service routine
stacked interrupts
no flush option
prefetch unit and store instructions
4-6
6-12
2-33
2-31
5-52
6-21
2-10
5-19
5-31
6-12
5-52
6-5
5-63
5-19
5-63
5-27
6-33
5-30
6-37
5-76
6-38
6-26
2-30
5-51
5-33
2-32
2-5
5-51
5-28
5-31
5-8
5-19
2-5
5-40
6-37
5-24
2-30
5-56
5-68
5-53
2-33
5-30
5-63
5-66
,
2-6
2-3
5-59
5-64
,
5-56
6-38
,
5-59
5-66