LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 43

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.9 SCSI Bus Interface
Step 3. If any wide transfers have been performed using the Chained
Synchronous SCSI Receive –
Step 1. If the DMA FIFO size is set to 88 bytes, subtract the seven
Step 2. Read bits [7:4] of the
Step 3. If any wide transfers have been performed using the Chained
The LSI53C875 supports both SE and differential operation.
All SCSI signals are active low. The LSI53C875 contains the SE output
drivers and can be connected directly to the SCSI bus. Each output is
isolated from the power supply to ensure that a powered down
LSI53C875 has no effect on an active SCSI bus (CMOS “voltage
feed-through” phenomena). TolerANT technology provides signal filtering
at the inputs of SREQ/ and SACK/ to increase immunity to signal
reflections.
PCI Cache Mode
Move instruction, read the Wide SCSI Receive bit
Control Two
in the
least significant bits of the
from the 7-bit value of the
the result with 0x7F for a byte count between 0 and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
Test Five (CTEST5)
bits of the
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO
register. AND the result with 0x3FF for a byte count between
0 and 536.
bit 4 of the
representation of the number of valid bytes in the SCSI FIFO,
to determine if any bytes are left in the SCSI FIFO.
Move instruction, read the Wide SCSI Receive bit
Control Two
in the
SCSI Wide Residue (SWIDE)
SCSI Wide Residue (SWIDE)
DMA Byte Counter (DBC)
SCSI Status Two (SSTAT2)
(SCNTL2), bit 0) to determine whether a byte is left
(SCNTL2), bit 0) to determine whether a byte is left
register), subtract the 10 least significant
SCSI Status One (SSTAT1)
DMA FIFO (DFIFO)
DMA Byte Counter (DBC)
register.
register.
register from the 10-bit
register, the binary
register. AND
register and
(SCSI
(SCSI
register
Chip
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