LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 163

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

31
x
x
x
x
x
x
x
Registers: 0x34–0x37 (0xB4–0xB7)
Scratch Register A (SCRATCHA)
Read/Write
SCRATCHA
Register: 0x38 (0xB8)
DMA Mode (DMODE)
Read/Write
BL[1:0]
x
x
7
0
BL[1:0]
x
x
x
6
0
Scratch Register A
This is a general purpose, user-definable scratch pad
register. Apart from CPU access, only Register
Read/Write and Memory Moves into the SCRATCH
register alter its contents. The LSI53C875 cannot fetch
SCRIPTS instructions from this location. When bit 3 in
the
contains the memory-mapped base address of the
operating registers. Setting
only causes the base address to appear in this register.
Any information that was previously in the register
remains intact. Any writes to this register while
Two (CTEST2),
Scratch Register A (SCRATCHA)
value of this register is indeterminate.
Burst Length
These bits control the maximum number of transfers
performed per bus ownership, regardless of whether the
transfers are back-to-back, burst, or a combination of
both. The LSI53C875 asserts the Bus Request (REQ/)
output when the DMA FIFO can accommodate a transfer
of at least one burst size of data. Bus Request (REQ/) is
also asserted during start-of-transfer and end-of-transfer
cleanup and alignment, even if less than a full burst of
transfers is performed. The LSI53C875 inserts a “fairness
delay” of four CLKs between burst length transfers (as
x
x
Chip Test Two (CTEST2)
SIOM
SCRATCHA
x
5
0
x
x
DIOM
x
4
0
bit 3 is set passes through to the actual
x
x
x
ERL
3
0
x
Chip Test Two (CTEST2)
x
register is set, this register
ERMP
x
register. The power-up
2
0
x
x
x
BOF
1
0
x
x
Chip Test
x
MAN
[31:0]
0
0
x
bit 3
[7:6]
5-47
0
x