LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 168

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-52
IRQM
STD
IRQD
SCSI Operating Registers
continues fetching and executing instructions until an
interrupt condition occurs. For normal SCSI SCRIPTS
operation, keep this bit clear. To restart the LSI53C875
after it generates a SCRIPTS Step interrupt, read the
Interrupt Status (ISTAT)
registers to recognize and clear the interrupt. Then set
the START DMA bit in this register.
IRQ Mode
When set, this bit will enable a totem pole driver for the
IRQ pin. When cleared, this bit enables an open drain
driver for the IRQ pin with a internal weak pull-up. This
bit is reset at power up. The bit should remain cleared to
retain full PCI compliance.
Start DMA Operation
The LSI53C875 fetches a SCSI SCRIPTS instruction
from the address contained in the
(DSP)
the LSI53C875 is in one of the following modes:
When the LSI53C875 is executing SCRIPTS in manual
start mode, the Start DMA bit must to be set to start
instruction fetches, but need not be set again until an
interrupt occurs. When the LSI53C875 is in single step
mode, the Start DMA bit needs to be set to restart
execution of SCRIPTS after a single step interrupt.
IRQ Disable
Setting this bit disables the IRQ pin. Clearing the bit
enables normal operation. As with any other register
other than ISTAT, this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS exe-
cution. For more information on the use of this bit in inter-
rupt handling, see
Manual start mode – Bit 0 in the
(DMODE)
Single step mode – Bit 4 in the
register is set
register when this bit is set. This bit is required if
register is set
Chapter 2, “Functional Description.”
and
DMA Status (DSTAT)
DMA SCRIPTS Pointer
DMA Control (DCNTL)
DMA Mode
3
2
1