LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 191

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

Register: 0x4F (0xCF)
SCSI Test Three (STEST3)
Read/Write
TE
STR
TE
7
0
STR
6
0
set this bit for access to the SCSI bit-level registers
Output Data Latch
(SBCL), and input registers.
TolerANT Enable
Setting this bit enables the active negation portion of
TolerANT technology. Active negation causes the SCSI
Request, Acknowledge, Data, and Parity signals to be
actively deasserted, instead of relying on external
pull-ups, when the LSI53C875 is driving these signals.
Active deassertion of these signals occurs only when the
LSI53C875 is in an information transfer phase. When
operating in a differential environment or at fast SCSI
timings, TolerANT Active negation should be enabled to
improve setup and deassertion times. Active negation is
disabled after reset or when this bit is cleared. For more
information on TolerANT technology, refer to
“General Description.”
SCSI Control Three (SCNTL3)
SCSI FIFO Test Read
Setting this bit places the SCSI core into a test mode in
which the SCSI FIFO is easily read. Reading the least
significant byte of the
register causes the FIFO to unload. The functions are
summarized in the table below.
Register
SODL0
SODL1
Name
SODL
HSC
5
0
Operation
DSI
Register
4
0
Read
Read
Read
(SODL),
SCSI Output Data Latch (SODL)
Set this bit if the ULTRA bit in
S16
3
0
SCSI Bus Control Lines
FIFO Bits
[15:0]
[15:8]
[7:0]
is set.
TTM
2
0
CSF
Function
1
0
Unload
Unload
None
FIFO
Chapter 1,
STW
SCSI
0
0
5-75
7
6