LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 159

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

BL2
BO[9:8]
Register: 0x23 (0xA3)
Chip Test Six (CTEST6)
Read/Write
DF[7:0]
7
0
0
the DMAWR signal indicates that data is transferred from
the SCSI bus to the host bus. Deasserting the DMAWR
signal transfers data from the host bus to the SCSI bus.
Burst Length
This bit works with bits 6 and 7 in the
(DMODE)
complete definitions of this field, refer to the descriptions
of
if an 88-byte FIFO is selected by clearing the DMA FIFO
size bit.
Byte Offset
These are the upper two bits of the DMA FIFO byte offset
counter. The entire field is described under the
FIFO (DFIFO)
DMA FIFO
Writing to this register writes data to the appropriate byte
lane of the DMA FIFO as determined by the FBL bits in
the
register unloads data from the appropriate byte lane of
the DMA FIFO as determined by the FBL bits in the
Test Four (CTEST4)
loaded into the top of the FIFO. Data read out of the FIFO
is taken from the bottom. To prevent DMA data from
being corrupted, this register should not be accessed
before starting or restarting SCRIPTS operation. Write
this register only when testing the DMA FIFO using the
Chip Test Four (CTEST4)
while the test mode is not enabled produces unexpected
results.
DMA Mode (DMODE)
Chip Test Four (CTEST4)
0
register to determine the burst length. For
register, bits [7:0].
0
DF
register. Data written to the FIFO is
0
bits 6 and 7. This bit is disabled
register. Writes to this register
register. Reading this
0
DMA Mode
0
DMA
Chip
0
0
[1:0]
[7:0]
5-43
2