LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 144

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

5-28
Table 5.5
SDP0L
MSG
C/D
I/O
SCSI Operating Registers
(SSTAT2 Bit 4)
FF4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCSI Synchronous Data FIFO Word Count
Latched SCSI Parity
This bit reflects the SCSI parity signal (SDP0/),
corresponding to the data latched in the
Latch
the least significant byte of the
(SIDL)
is set when the parity signal is active.
SCSI MSG/ Signal
SCSI C_D/ Signal
SCSI I_O/ Signal
These SCSI phase status bits are latched on the
asserting edge of SREQ/ when operating in either initiator
or target mode. These bits are set when the
corresponding signal is active. They are useful when
operating in low level mode.
(SIDL). It changes when a new byte is latched into
FF3
register. This bit is active high, in other words, it
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
FF2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
FF1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
FF0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SCSI Input Data Latch
Bytes or Words
SCSI Input Data
SCSI FIFO
in the
10
11
12
13
14
15
16
0
1
2
3
4
5
6
7
8
9
3
2
1
0