ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 128
ATMEGA2561V
Manufacturer Part Number
ATMEGA2561V
Description
8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA2561V.pdf
(449 pages)
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Timer/Counter Timing
Diagrams
128
ATmega640/1280/1281/2560/2561
•
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set. Figure 44 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 44. Timer/Counter Timing Diagram, no Prescaling
Figure 45 shows the same timing data, but with the prescaler enabled.
Figure 45. Timer/Counter Timing Diagram, with Prescaler (f
Figure 46 shows the setting of OCF0B in all modes and OCF0A in all modes except
CTC mode and PWM mode, where OCR0A is TOP.
Figure 46. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
TCNTn
TCNTn
TCNTn
(clk
(clk
(clk
OCRnx
TOVn
TOVn
OCFnx
clk
clk
clk
clk
clk
clk
I/O
I/O
I/O
Match. To ensure symmetry around BOTTOM the OCn value at MAX must
correspond to the result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR0A, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
I/O
I/O
I/O
Tn
Tn
Tn
/1)
/8)
/8)
OCRnx - 1
MAX - 1
MAX - 1
OCRnx
MAX
MAX
OCRnx Value
OCRnx + 1
BOTTOM
BOTTOM
clk_I/O
/8)
T0
) is therefore
2549K–AVR–01/07
BOTTOM + 1
BOTTOM + 1
OCRnx + 2
clk_I/O
/8)
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