ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 444

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

iv
ATmega640/1280/1281/2560/2561
2-wire Serial Interface...................................................................... 245
AC – Analog Comparator ................................................................ 275
ADC – Analog to Digital Converter ................................................ 279
JTAG Interface and On-chip Debug System ................................. 301
IEEE 1149.1 (JTAG) Boundary-scan .............................................. 308
Overview........................................................................................................... 236
USART MSPIM vs. SPI .................................................................................... 236
Clock Generation .............................................................................................. 236
SPI Data Modes and Timing............................................................................. 237
Frame Formats ................................................................................................. 238
Data Transfer.................................................................................................... 240
USART MSPIM Register Description ............................................................... 242
Features............................................................................................................ 245
2-wire Serial Interface Bus Definition................................................................ 245
Data Transfer and Frame Format ..................................................................... 246
Multi-master Bus Systems, Arbitration and Synchronization ............................ 249
Overview of the TWI Module ............................................................................ 251
Using the TWI ................................................................................................... 253
Transmission Modes......................................................................................... 256
Multi-master Systems and Arbitration............................................................... 269
Register Description ......................................................................................... 271
Analog Comparator Multiplexed Input .............................................................. 276
Register Description ......................................................................................... 277
Features............................................................................................................ 279
Operation .......................................................................................................... 281
Starting a Conversion ....................................................................................... 281
Prescaling and Conversion Timing ................................................................... 282
Changing Channel or Reference Selection ...................................................... 286
ADC Noise Canceler......................................................................................... 287
ADC Conversion Result.................................................................................... 292
Register Description ......................................................................................... 294
Overview........................................................................................................... 301
TAP - Test Access Port .................................................................................... 303
Using the Boundary-scan Chain ....................................................................... 305
Using the On-chip Debug System .................................................................... 305
On-chip Debug Specific JTAG Instructions ...................................................... 306
Using the JTAG Programming Capabilities ...................................................... 306
Bibliography ...................................................................................................... 306
On-chip Debug Related Register in I/O Memory .............................................. 307
Features............................................................................................................ 308
System Overview.............................................................................................. 308
2549K–AVR–01/07