ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 86

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

86
ATmega640/1280/1281/2560/2561
Figure 34. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the suc-
ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a
single signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 35. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock
period.
Figure 35. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and
define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
PINxn
PINxn
r17
r16
r17
out PORTx, r16
XXX
t
pd, max
0x00
0x00
XXX
nop
t
pd
t
0xFF
pd, min
in r17, PINx
in r17, PINx
2549K–AVR–01/07
0xFF
0xFF