ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 173

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Register Description
GTCCR – General
Timer/Counter Control
Register
2549K–AVR–01/07
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
An external clock source can not be prescaled.
Figure 62. Prescaler for synchronous Timer/Counters
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keep-
ing the corresponding prescaler reset signals asserted. This ensures that the
corresponding Timer/Counters are halted and can be configured to the same value with-
out the risk of one of them advancing during configuration. When the TSM bit is written
to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the
Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4
and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by
hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1,
Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler and a
reset of this prescaler will affect all timers.
Bit
0x23 (0x43)
Read/Write
Initial Value
PSR10
clk
CSn0
CSn1
CSn2
Tn
Tn
I/O
Synchronization
Synchronization
TSM
R/W
7
0
R
6
–
0
ATmega640/1280/1281/2560/2561
TIMER/COUNTERn CLOCK SOURCE
R
5
–
0
clk_I/O
clk
Clear
Tn
/2.5.
R
4
–
0
R
3
–
0
CSn0
CSn1
CSn2
R
2
–
0
TIMER/COUNTERn CLOCK SOURCE
PSRASY PSRSYNC
R/W
1
0
clk
R/W
Tn
0
0
GTCCR
173