ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 79

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

EICRB – External Interrupt
Control Register B
EIMSK – External Interrupt
Mask Register
2549K–AVR–01/07
• Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the
external pins that activate the interrupts are defined in Table 36. The value on the
INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected,
pulses that last longer than one clock period will generate an interrupt. Shorter pulses
are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be
lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
Table 36. Interrupt Sense Control
Note:
• Bits 7:0 – INT7:0: External Interrupt Request 7 - 0 Enable
When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether
the external interrupt is activated on rising or falling edge or level sensed. Activity on any
of these pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
Bit
(0x6A)
Read/Write
Initial Value
Bit
0x1D (0x3D)
Read/Write
Initial Value
ISCn1
Bits
0
0
1
1
1. n = 7, 6, 5 or 4.
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its
Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when
the bits are changed.
0
1
0
1
ISC71
INT7
R/W
R/W
7
0
7
0
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt
request.
The rising edge between two samples of INTn generates an interrupt
request.
ISC70
INT6
R/W
R/W
ATmega640/1280/1281/2560/2561
6
0
6
0
ISC61
INT5
R/W
R/W
5
0
5
0
(1)
ISC60
INT4
R/W
R/W
4
0
4
0
ISC51
INT3
R/W
R/W
3
0
3
0
ISC50
INT2
R/W
R/W
2
0
2
0
ISC41
INT1
R/W
R/W
1
0
1
0
ISC40
INT0
R/W
R/W
0
0
0
0
EICRB
EIMSK
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