ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 169

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

TIMSK1 – Timer/Counter 1
Interrupt Mask Register
TIMSK3 – Timer/Counter 3
Interrupt Mask Register
TIMSK4 – Timer/Counter 4
Interrupt Mask Register
TIMSK5 – Timer/Counter 5
Interrupt Mask Register
2549K–AVR–01/07
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
OCFnC Flag, located in TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
OCFnB Flag, located in TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 69.) is executed when the
OCFnA Flag, located in TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 69.) is executed when the TOVn Flag, located
in TIFRn, is set.
Bit
(0x6F)
Read/Write
Initial Value
Bit
(0x71)
Read/Write
Initial Value
Bit
(0x72)
Read/Write
Initial Value
Bit
(0x73)
Read/Write
Initial Value
R
R
R
R
7
–
0
7
–
0
7
–
0
7
–
0
ATmega640/1280/1281/2560/2561
R
R
R
R
6
–
0
6
–
0
6
–
0
6
–
0
ICIE1
ICIE3
ICIE4
ICIE5
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
OCIE1C
OCIE3C
OCIE4C
OCIE5C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCIE1B
OCIE3B
OCIE4B
OCIE5B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE1A
OCIE3A
OCIE4A
OCIE5A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOIE1
TOIE3
TOIE4
TOIE5
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TIMSK1
TIMSK3
TIMSK4
TIMSK5
169