ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 78

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Register Description
EICRA – External Interrupt
Control Register A
78
ATmega640/1280/1281/2560/2561
The External Interrupt Control Register A contains control bits for interrupt sense
control.
• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the
external pins that activate the interrupts are defined in Table 34. Edges on INT3:0 are
registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width
given in Table 35 will generate an interrupt. Shorter pulses are not guaranteed to gener-
ate an interrupt. If low level interrupt is selected, the low level must be held until the
completion of the currently executing instruction to generate an interrupt. If enabled, a
level triggered interrupt will generate an interrupt request as long as the pin is held low.
When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to
first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the
ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a
logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-
enabled.
Table 34. Interrupt Sense Control
Note:
Table 35. Asynchronous External Interrupt Characteristics
Bit
(0x69)
Read/Write
Initial Value
Symbol
ISCn1
Bits
t
0
0
1
1
INT
1. n = 3, 2, 1or 0.
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its
Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when
the bits are changed.
Parameter
Minimum pulse width for
asynchronous external interrupt
0
1
0
1
ISC31
R/W
7
0
Description
The low level of INTn generates an interrupt request.
Any edge of INTn generates asynchronously an interrupt request.
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
ISC30
R/W
6
0
ISC21
R/W
5
0
(1)
ISC20
R/W
4
0
ISC11
R/W
Condition
3
0
ISC10
R/W
2
0
Min
ISC01
R/W
1
0
Typ
50
ISC00
R/W
0
0
2549K–AVR–01/07
Max
EICRA
Units
ns