ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 262
ATMEGA2561V
Manufacturer Part Number
ATMEGA2561V
Description
8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA2561V.pdf
(449 pages)
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Slave Receiver Mode
262
ATmega640/1280/1281/2560/2561
Figure 103. Formats and States in the Master Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a Master Trans-
mitter (see Figure 104). All the status codes mentioned in this section assume that the
prescaler bits are zero or are masked to zero.
Figure 104. Data transfer in Slave Receiver mode
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
TWAR
value
SDA
From master to slave
From slave to master
SCL
$08
S
SLA
TWA6
Device 1
RECEIVER
SLAVE
R
TWA5
MR
TRANSMITTER
A or A
Device 2
DATA
$40
$48
$38
$68
MASTER
A
A
A
$78
Other master
Other master
TWA4
n
continues
continues
Device’s Own Slave Address
P
$B0
DATA
Device 3
A
TWA3
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
........
$50
$38
To corresponding
states in slave mode
A
A
TWA2
Device n
Other master
DATA
continues
V
CC
$58
TWA1
A
R1
$10
P
R
S
TWA0
R2
2549K–AVR–01/07
SLA
TWGCE
W
R
MT
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