ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 170

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

TIFR1 – Timer/Counter1
Interrupt Flag Register
TIFR3 – Timer/Counter3
Interrupt Flag Register
TIFR4 – Timer/Counter4
Interrupt Flag Register
TIFR5 – Timer/Counter5
Interrupt Flag Register
170
ATmega640/1280/1281/2560/2561
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture
Register (ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is
set when the counter reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-
natively, ICFn can be cleared by writing a logic one to its bit location.
• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Out-
put Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is
executed. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Out-
put Compare Register B (OCRnB).
Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.
OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is
executed. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn value matches the Out-
put Compare Register A (OCRnA).
Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.
Bit
0x16 (0x36)
Read/Write
Initial Value
Bit
0x18 (0x38)
Read/Write
Initial Value
Bit
0x19 (0x39)
Read/Write
Initial Value
Bit
0x1A (0x3A)
Read/Write
Initial Value
R
R
R
R
7
–
0
7
–
0
7
–
0
7
–
0
R
R
R
R
6
–
0
6
–
0
6
–
0
6
–
0
ICF1
ICF3
ICF4
ICF5
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
OCF1C
OCF3C
OCF4C
OCF5C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCF1B
OCF3B
OCF4B
OCF5B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCF1A
OCF3A
OCF4A
OCF5A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOV1
TOV3
TOV4
TOV5
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
2549K–AVR–01/07
TIFR1
TIFR3
TIFR4
TIFR5