ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 285
ATMEGA2561V
Manufacturer Part Number
ATMEGA2561V
Description
8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA2561V.pdf
(449 pages)
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Differential Channels
2549K–AVR–01/07
Table 126. ADC Conversion Time
When using differential channels, certain aspects of the conversion need to be taken
into consideration.
Differential conversions are synchronized to the internal clock CK
ADC clock. This synchronization is done automatically by the ADC interface in such a
way that the sample-and-hold occurs at a specific phase of CK
ated by the user (i.e., all single conversions, and the first free running conversion) when
CK
clock cycles from the next prescaled clock cycle). A conversion initiated by the user
when CK
nism. In Free Running mode, a new conversion is initiated immediately after the
previous conversion completes, and since CK
started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the
ADC must be switched off between conversions. When Auto Triggering is used, the
ADC prescaler is reset before the conversion is started. Since the stage is dependent of
a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling
and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to
“0” then to “1”), only extended conversions are performed. The result from the extended
conversions will be valid. See “Prescaling and Conversion Timing” on page 282 for tim-
ing details.
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
ADC2
is low will take the same amount of time as a single ended conversion (13 ADC
ADC2
is high will take 14 ADC clock cycles due to the synchronization mecha-
ATmega640/1280/1281/2560/2561
Sample & Hold (Cycles
from Start of Conversion)
1.5/2.5
13.5
1.5
2
ADC2
is high at this time, all automatically
ADC2
Conversion Time
ADC2
. A conversion initi-
(Cycles)
equal to half the
13/14
13.5
25
13
285
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