ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 314
ATMEGA2561V
Manufacturer Part Number
ATMEGA2561V
Description
8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA2561V.pdf
(449 pages)
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Boundary-scan Related
Register in I/O Memory
MCUCR – MCU Control
Register
MCUSR – MCU Status
Register
314
ATmega640/1280/1281/2560/2561
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling
or enabling of the JTAG interface, a timed sequence must be followed when changing
this bit: The application software must write this bit to the desired value twice within four
cycles to change its value. Note that this bit must not be altered when using the On-chip
Debug system.
The MCU Status Register provides information on which reset source caused an MCU
reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x34 (0x54)
Read/Write
Initial Value
JTD
R/W
R
7
0
7
–
0
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
JTRF
PUD
R/W
R/W
4
0
4
WDRF
R/W
R
3
–
0
3
See Bit Description
BORF
R/W
2
–
R
0
2
EXTRF
IVSEL
R/W
R/W
1
0
1
PORF
IVCE
R/W
R/W
2549K–AVR–01/07
0
0
0
MCUCR
MCUSR
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