ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 236

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

USART in SPI Mode
Overview
USART MSPIM vs. SPI
Clock Generation
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ATmega640/1280/1281/2560/2561
The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) can be set to a master SPI compliant mode of operation. The Master SPI
Mode (MSPIM) has the following features:
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Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of
operation the SPI master control logic takes direct control over the USART resources.
These resources include the transmitter and receiver shift register and buffers, and the
baud rate generator. The parity generator and checker, the data and clock recovery
logic, and the RX and TX control logic is disabled. The USART RX and TX control logic
is replaced by a common SPI transfer control logic. However, the pin control logic and
interrupt generation logic is identical in both modes of operation.
The I/O register locations are the same in both modes. However, some of the functional-
ity of the control registers changes when using MSPIM.
The AVR USART in MSPIM mode is fully compatible with the AVR SPI regarding:
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However, since the USART in MSPIM mode reuses the USART resources, the use of
the USART in MSPIM mode is somewhat different compared to the SPI. In addition to
differences of the control register bits, and that only master operation is supported by
the USART in MSPIM mode, the following features differ between the two modules:
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A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 116 on
page 244
The Clock Generation logic generates the base clock for the Transmitter and Receiver.
For USART MSPIM mode of operation only internal clock generation (i.e. master opera-
tion) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must
therefore be set to one (i.e. as output) for the USART in MSPIM to operate correctly.
Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled
(i.e. TXENn and RXENn bit set to one).
Full Duplex, Three-wire Synchronous Data Transfer
Master Operation
Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
LSB First or MSB First Data Transfer (Configurable Data Order)
Queued Operation (Double Buffered)
High Resolution Baud Rate Generator
High Speed Operation (fXCKmax = fCK/2)
Flexible Interrupt Generation
Master mode timing diagram.
The UCPOLn bit functionality is identical to the SPI CPOL bit.
The UCPHAn bit functionality is identical to the SPI CPHA bit.
The UDORDn bit functionality is identical to the SPI DORD bit.
The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI
has no buffer.
The USART in MSPIM mode receiver includes an additional buffer level.
The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
The SPI double speed mode (SPI2X) bit is not included. However, the same effect is
achieved by setting UBRRn accordingly.
Interrupt timing is not compatible.
Pin control differs due to the master only operation of the USART in MSPIM mode.
2549K–AVR–01/07