ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 229

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

UCSRnC – USART Control
and Status Register n C
2549K–AVR–01/07
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty
interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-
mal port operation for the TxDn pin when enabled. The disabling of the Transmitter
(writing TXENn to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register
do not contain data to be transmitted. When disabled, the Transmitter will no longer
override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames
with nine data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDRn.
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in Table 104.
Table 104. UMSELn Bits Settings
Note:
Bit
Read/Write
Initial Value
UMSELn1
1. See “USART in SPI Mode” on page 236 for full description of the Master SPI Mode
0
0
1
1
(MSPIM) operation
UMSELn1
R/W
7
0
UMSELn0
R/W
ATmega640/1280/1281/2560/2561
UMSELn0
6
0
0
1
0
1
UPMn1
R/W
5
0
UPMn0
R/W
Mode
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)
4
0
USBSn
R/W
3
0
UCSZn1
R/W
2
1
(1)
UCSZn0
R/W
1
1
UCPOLn
R/W
0
0
UCSRnC
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