ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 278

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

DIDR1 – Digital Input Disable
Register 1
278
ATmega640/1280/1281/2560/2561
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to
be triggered by the Analog Comparator. The comparator output is in this case directly
connected to the input capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When
written logic zero, no connection between the Analog Comparator and the input capture
function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-
rupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator inter-
rupt. The different settings are shown in Table 125.
Table 125. ACIS1/ACIS0 Settings
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-
abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt
can occur when the bits are changed.
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled.
The corresponding PIN Register bit will always read as zero when this bit is set. When
an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not
needed, this bit should be written logic one to reduce power consumption in the digital
input buffer.
Bit
(0x7F)
Read/Write
Initial Value
ACIS1
0
0
1
1
R
7
–
0
ACIS0
0
1
0
1
R
6
–
0
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Interrupt Mode
R
5
–
0
R
4
–
0
R
3
–
0
R
2
–
0
AIN1D
R/W
1
0
AIN0D
R/W
0
0
2549K–AVR–01/07
DIDR1