ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 244

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

UCSRnC – USART MSPIM
Control and Status Register n
C
UBRRnL and UBRRnH –
USART MSPIM Baud Rate
Registers
244
ATmega640/1280/1281/2560/2561
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 115. See
“UCSRnC – USART Control and Status Register n C” on page 229 for full description of
the normal USART operation. The MSPIM is enabled when both UMSELn bits are set to
one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write operation
where the MSPIM is enabled.
Table 115. UMSELn Bits Settings
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB
of the data word is transmitted first. Refer to the Frame Formats section page 4 for
details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing
(last) edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn
and UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data
Modes and Timing section page 4 for details.
The function and bit description of the baud rate registers in MSPI mode is identical to
normal USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers”
on page 231.
Table 116. Comparison of USART in MSPIM mode and SPI pins.
Bit
Read/Write
Initial Value
UMSELn1
0
0
1
1
USART_MSPIM
XCKn
RxDn
TxDn
(N/A)
UMSELn1
R/W
7
0
1
0
1
UMSELn0
UMSELn0
0
R/W
6
0
MOSI
MISO
SCK
SPI
SS
R
5
0
-
R
4
0
-
Mode
Asynchronous USART
(Reserved)
Master SPI (MSPIM)
Synchronous USART
Comment
Master Out only
Master In only
(Functionally identical)
Not supported by USART in MSPIM
R
3
0
-
UDORDn
R/W
2
1
UCPHAn
R/W
1
1
UCPOLn
R/W
0
0
2549K–AVR–01/07
UCSRnC