ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 172

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Timer/Counter 0, 1, 3, 4, and 5 Prescaler
Internal Clock Source
Prescaler Reset
External Clock Source
172
ATmega640/1280/1281/2560/2561
Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to
all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or 5.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation, with a maximum Timer/Counter clock frequency
equal to system clock frequency (f
caler can be used as a clock source. The prescaled clock has a frequency of either
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of
the Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implica-
tions for situations where a prescaled clock is used. One example of prescaling artifacts
occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the timer is enabled to the first count occurs
can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,
256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program
execution. However, care must be taken if the other Timer/Counter that shares the
same prescaler also uses prescaling. A prescaler reset will affect the prescaler period
for all Timer/Counters it is connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector. Fig-
ure 61 shows a functional equivalent block diagram of the Tn synchronization and edge
detector logic. The registers are clocked at the positive edge of the internal system clock
(
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 61. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at
least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse
is generated.
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
CLK_I/O
clk
Tn
I/O
Tn
clk
). The latch is transparent in the high period of the internal system clock.
). The Tn pin is sampled once every system clock cycle by the pin synchronization
I/O
/8, f
CLK_I/O
D
LE
/64, f
Q
CLK_I/O
Synchronization
D
/256, or f
Q
CLK_I/O
CLK_I/O
Tn
ExtClk
pulse for each positive (CSn2:0 = 7) or negative
). Alternatively, one of four taps from the pres-
/1024.
< f
clk_I/O
/2) given a 50/50% duty cycle. Since
D
Q
Edge Detector
2549K–AVR–01/07
Tn_sync
(To Clock
Select Logic)