ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 315
ATMEGA2561V
Manufacturer Part Number
ATMEGA2561V
Description
8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA2561V.pdf
(449 pages)
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ATmega640/1280/1281/25
60/2561 Boundary-scan
Order
Boundary-scan
Description Language
Files
2549K–AVR–01/07
Table 132 shows the Scan order between TDI and TDO when the Boundary-scan chain
is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit
scanned out. The scan order follows the pin-out order as far as possible. Therefore, the
bits of Port A and Port K is scanned in the opposite bit order of the other ports. Excep-
tions from the rules are the Scan chains for the analog circuits, which constitute the
most significant bits of the scan chain regardless of which physical pin they are con-
nected to. In Figure 132, PXn. Data corresponds to FF0, PXn. Control corresponds to
FF1, PXn. Bit 4, 5, 6 and 7 of Port F is not in the scan chain, since these pins constitute
the TAP pins when the JTAG is enabled.
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable
devices in a standard format used by automated test-generation software. The order
and function of bits in the Boundary-scan Data Register are included in this description.
BSDL files are available for ATmega1281/2561 and ATmega640/1280/2560.
Table 132. ATmega640/1280/2560 Boundary-scan Order
Bit Number
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
Signal Name
PG5.Data
PG5.Control
PE0.Data
PE0.Control
PE1.Data
PE1.Control
PE2.Data
PE2.Control
PE3.Data
PE3.Control
PE4.Data
PE4.Control
PE5.Data
PE5.Control
PE6.Data
PE6.Control
PE7.Data
PE7.Control
PH0.Data
PH0.Control
PH1.Data
PH1.Control
PH2.Data
PH2.Control
ATmega640/1280/1281/2560/2561
Module
Port G
Port E
Port H
315
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