ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 237

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

SPI Data Modes and
Timing
2549K–AVR–01/07
The internal clock generation used in MSPIM mode is identical to the USART synchro-
nous master mode. The baud rate or UBRRn setting can therefore be calculated using
the same equations, see Table 113:
Table 113. Equations for Calculating Baud Rate Register Setting
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial
data, which are determined by control bits UCPHAn and UCPOLn. The data transfer
timing diagrams are shown in Figure 89. Data bits are shifted out and latched in on
opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize.
The UCPOLn and UCPHAn functionality is summarized in Table 114. Note that chang-
ing the setting of any of these bits will corrupt all ongoing communication for both the
Receiver and Transmitter.
Table 114. UCPOLn and UCPHAn Functionality-
Operating Mode
Synchronous Master
mode
BAUD Baud rate (in bits per second, bps)
f
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095)
OSC
UCPOLn
0
0
1
1
1. The baud rate is defined to be the transfer rate in bit per second (bps)
System Oscillator clock frequency
UCPHAn
0
1
0
1
Equation for Calculating Baud
ATmega640/1280/1281/2560/2561
BAUD
SPI Mode
=
0
1
2
3
Rate
-------------------------------------- -
2 UBRRn
(
(1)
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
+
1
)
Equation for Calculating
UBRRn
UBRRn Value
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Trailing Edge
=
------------------- - 1
2BAUD
f
OSC
–
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