ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 207

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

SPSR – SPI Status Register
2549K–AVR–01/07
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f
Table 100. Relationship Between SCK and the Oscillator Frequency
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low
when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing
the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register
with WCOL set, and then accessing the SPI Data Register.
• Bit 5:1 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode (see Table 100). This means that the minimum SCK period
will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only
guaranteed to work at f
The SPI interface on the ATmega640/1280/1281/2560/2561 is also used for program
memory and EEPROM downloading or uploading. See “Serial Downloading” on page
356 for serial programming and verification.
Bit
0x2D (0x4D)
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
SPIF
R
7
0
osc
is shown in the following table:
WCOL
osc
SPR1
ATmega640/1280/1281/2560/2561
R
6
0
0
0
1
1
0
0
1
1
/4 or lower.
R
5
–
0
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
3
–
R
0
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
R
1
–
0
SPI2X
R/W
0
0
SPSR
207