ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 211

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Clock Generation
2549K–AVR–01/07
The Clock Generation logic generates the base clock for the Transmitter and Receiver.
The USARTn supports four modes of clock operation: Normal asynchronous, Double
Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn
bit in USART Control and Status Register C (UCSRnC) selects between asynchronous
and synchronous operation. Double Speed (asynchronous mode only) is controlled by
the U2Xn found in the UCSRnA Register. When using synchronous mode (UMSELn =
1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the
clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only
active when using synchronous mode.
Figure 83 shows a block diagram of the clock generation logic.
Figure 83. Clock Generation Logic, Block Diagram
Signal description:
txclk
rxclk
xcki
xcko
f
OSC
DDR_XCK
XCK
Pin
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
ATmega640/1280/1281/2560/2561
UBRR+1
fosc
Detector
UCPOL
Edge
/2
/4
/2
DDR_XCK
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
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