ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 16

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Instruction Execution
Timing
16
ATmega640/1280/1281/2560/2561
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
source for the chip. No internal clock division is used.
Figure 10 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results
for functions per cost, functions per clocks, and functions per power-unit.
Figure 10. The Parallel Instruction Fetches and Instruction Executions
Figure 11 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 11. Single Cycle ALU Operation
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
clk
clk
CPU
CPU
T1
T1
CPU
, directly generated from the selected clock
T2
T2
T3
T3
2549K–AVR–01/07
T4
T4