ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 311

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

BYPASS; 0xF
Boundary-scan Chain
Scanning the Digital Port Pins Figure 132 shows the Boundary-scan Cell for a bi-directional port pin. The pull-up func-
2549K–AVR–01/07
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
The Boundary-scan chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having off-chip connection.
tion is disabled during Boundary-scan when the JTAG IC contains EXTEST or
SAMPLE_PRELOAD. The cell consists of a bi-directional pin cell that combines the
three signals Output Control - OCxn, Output Data - ODxn, and Input Data - IDxn, into
only a two-stage Shift Register. The port and pin indexes are not used in the following
description
The Boundary-scan logic is not included in the figures in the datasheet. Figure 133
shows a simple digital port pin as described in the section “I/O-Ports” on page 83. The
Boundary-scan details from Figure 132 replaces the dashed box in Figure 133.
When no alternate port function is present, the Input Data - ID - corresponds to the
PINxn Register value (but ID has no synchronizer), Output Data corresponds to the
PORT Register, Output Control corresponds to the Data Direction - DD Register, and
the Pull-up Enable - PUExn - corresponds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 133 to
make the scan chain read the actual pin value. For analog function, there is a direct con-
nection from the external pin to the analog circuit. There is no scan chain on the
interface between the digital and the analog circuitry, but some digital control signal to
analog circuitry are turned off to avoid driving contention on the pads.
When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on
the port pins even if the CKOUT fuse is programmed. Even though the clock is output
when the JTAG IR contains SAMPLE_PRELOAD, the clock is not sampled by the
boundary scan.
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
ATmega640/1280/1281/2560/2561
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