ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 182

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Phase Correct PWM Mode
182
ATmega640/1280/1281/2560/2561
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase
correct PWM waveform generation option. The phase correct PWM mode is based on a
dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then
from TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when
MGM22:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC2x) is
cleared on the compare match between TCNT2 and OCR2x while upcounting, and set
on the compare match while downcounting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches
TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value
will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 70. The TCNT2 value is in the timing diagram shown as
a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes repre-
sent compare matches between OCR2x and TCNT2.
Figure 70. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT-
TOM. The Interrupt Flag can be used to generate an interrupt each time the counter
reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is
defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 90 on
page 192). The actual OC2x value will only be visible on the port pin if the data direction
for the port pin is set as output. The PWM waveform is generated by clearing (or setting)
the OC2x Register at the compare match between OCR2x and TCNT2 when the
counter increments, and setting (or clearing) the OC2x Register at compare match
TCNTn
OCnx
OCnx
Period
1
2
3
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
2549K–AVR–01/07