ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 94

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

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ATmega640/1280/1281/2560/2561
When the SPI0 is enabled as a master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt
source.
• SS/PCINT0 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured
as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a master, the data direction of this pin is
controlled by DDB0. When the pin is forced to be an input, the pull-up can still be con-
trolled by the PORTB0 bit.
Table 43 and Table 44 relate the alternate functions of Port B to the overriding signals
shown in Figure 36 on page 89. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute
the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE
INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt
source.
Table 43. Overriding Signals for Alternate Functions in PB7:PB4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PB7/OC0A/OC1C
0
0
0
0
OC0/OC1C ENABLE
OC0/OC1C
PCINT7 • PCIE0
1
PCINT7 INPUT
–
PB6/OC1B
0
0
0
0
OC1B ENABLE
OC1B
PCINT6 • PCIE0
1
PCINT6 INPUT
–
PB5/OC1A
0
0
0
0
OC1A ENABLE
OC1A
PCINT5 • PCIE0
1
PCINT5 INPUT
–
PB4/OC2A
0
0
0
0
OC2A ENABLE
OC2A
PCINT4 • PCIE0
1
PCINT4 INPUT
–
2549K–AVR–01/07