ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 20

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

SRAM Data Memory
Table 4 on page 21 shows how the ATmega640/1280/1281/2560/2561 SRAM Memory
is organized.
The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more periph-
eral units than can be supported within the 64 location reserved in the Opcode for the IN
and OUT instructions. For the Extended I/O space from $060 - $1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The first 4,608/8,704 Data Memory locations address both the Register File, the I/O
Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O Memory, then 416 loca-
tions of Extended I/O memory and the next 8,192 locations address the internal data
SRAM.
A n
o p t i o n a l
e x t e r n a l
d a t a
S R A M
c a n
b e
u s e d
w i t h
t h e
ATmega640/1280/1281/2560/2561. This SRAM will occupy an area in the remaining
address locations in the 64K address space. This area starts at the address following
the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the
lowest 4,608/8,704 bytes, so when using 64KB (65,536 bytes) of External Memory,
60,478/56,832 Bytes of External Memory are available. See “External Memory Inter-
face” on page 26 for details on how to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA
Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external
SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the
three-byte program counter is pushed and popped, and external memory access does
not take advantage of the internal pipe-line memory access. When external SRAM inter-
face is used with wait-state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the instruc-
tion set manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Dis-
placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register file, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 4,196/8,192 bytes of
internal data SRAM in the ATmega640/1280/1281/2560/2561 are all accessible through
ATmega640/1280/1281/2560/2561
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2549K–AVR–01/07