ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 224
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 224 of 826
- Download datasheet (20Mb)
24.10 Master Mode
24.10.1
24.10.2
Figure 24-5. Master Mode Typical Application Block Diagram
24.10.3
24.10.4
32058J-AVR32-04/11
Definition
Application Block Diagram
Programming Master Mode
Master Transmitter Mode
Rp: Pull up value as given by the I²C Standard
Host with
Interface
TWI
The Master is the device which starts a transfer, generates a clock and stops it.
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
After the master initiates a Start condition when writing into the Transmit Holding Register, THR,
it sends a 7-bit slave address, configured in the Master Mode register (DADR in MMR), to notify
the slave device. The bit following the slave address indicates the transfer direction, 0 in this
case (MREAD = 0 in MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK in the status register if the slave does not acknowledge the byte. As
with the other status bits, an interrupt can be generated if enabled in the interrupt enable register
(IER). If the slave acknowledges the byte, the data written in the THR, is then shifted in the inter-
nal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new
write in the THR. When no more data is written into the THR, the master generates a stop condi-
tion to end the transfer. The end of the complete transfer is marked by the TXCOMP bit set to
one. See
TXRDY is used as Transmit Ready for the PDC transmit channel.
TWD
TWCK
access slave devices in read or write mode.
Serial EEPROM
Atmel TWI
Slave 1
Figure
24-6,
Figure
I²C RTC
Slave 2
24-7, and
Controller
I²C LCD
Slave 3
Figure 24-8 on page
I²C Temp.
Slave 4
Sensor
225.
Rp
Rp
AT32UC3A
VDD
224
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