ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 376
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 376 of 826
- Download datasheet (20Mb)
27.6.4.2
32058J–AVR32–04/11
– Null Pulse
– Read is Controlled by NRD (READ_MODE = 1):
Read Mode
Figure 27-10. No Setup, No Hold On NRD and NCS Read Signals
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
ings to know which signal rises first. The READ_MODE parameter in the MODE register of the
corresponding chip select indicates which signal of NRD and NCS controls the read operation.
Figure 27-11
read data is available t
NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate
that data is available with the rising edge of NRD. The SMC samples the read data internally on
the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro-
grammed waveform of NCS may be.
NBS0, NBS1,
A0, A1
CLK_SMC
A[25:2]
D[15:0]
NRD
NCS
shows the waveforms of a read operation of a typical asynchronous RAM. The
PACC
NCS_RD_PULSE
NRD_CYCLE
NRD_SETUP
after the falling edge of NRD, and turns to ‘Z’ after the rising edge of
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
AT32UC3A
376
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