ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 592
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 592 of 826
- Download datasheet (20Mb)
30.8.2.18
Offset:
Register Name:
Access Type:
Reset Value:
• HSB_ADDR: HSB Address
This field determines the HSB bus current address of a channel transfer.
The address set on the HSB address bus is HSB_ADDR rounded down to the nearest word-aligned address, i.e.
HSB_ADDR[1:0] is considered as 00b since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The software may write this field only when the Channel Enabled bit (CH_EN) of the UDDMAX_STATUS register is clear.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB
access byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word
boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel
buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either
determined by the end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFF_CLOSE_IN_EN) is
set.
32058J–AVR32–04/11
31
23
15
0
0
0
7
0
USB Device DMA Channel X HSB Address Register (UDDMAX_ADDR)
30
22
14
0
0
0
6
0
29
21
13
0
0
0
5
0
0x0314 + (X - 1) . 0x10
UDDMAX_ADDR, X in [1..6]
Read/Write
0x00000000
28
20
12
0
0
0
4
0
HSB_ADDR
HSB_ADDR
HSB_ADDR
HSB_ADDR
rwu
rwu
rwu
rwu
27
19
11
0
0
0
3
0
26
18
10
0
0
0
2
0
25
17
0
0
9
0
1
0
AT32UC3A
24
16
0
0
8
0
0
0
592
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