ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 774
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 774 of 826
- Download datasheet (20Mb)
38.9
These timings are given for worst case process, T = 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance.
Table 38-22. SMC Clock Signal.
Note:
Table 38-23. SMC Read Signals with Hold Settings
Note:
32058J–AVR32–04/11
Symbol
1/(t
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
CPSMC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
EBI Timings
1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
)
Parameter
Data Setup before NRD High
Data Hold after NRD High
NRD High to NBS0/A0 Change
NRD High to NBS1 Change
NRD High to NBS2/A1 Change
NRD High to NBS3 Change
NRD High to A2 - A25 Change
NRD High to NCS Inactive
NRD Pulse Width
Data Setup before NCS High
Data Hold after NCS High
NCS High to NBS0/A0 Change
NCS High to NBS0/A0 Change
NCS High to NBS2/A1 Change
NCS High to NBS3 Change
NCS High to A2 - A25 Change
NCS High to NRD Inactive
NCS Pulse Width
Parameter
SMC Controller Clock Frequency
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
NRD Controlled (READ_MODE = 1)
NRD Controlled (READ_MODE = 0)
(nrd hold length - ncs rd hold length) * t
ncs rd hold length - nrd hold length)* t
ncs rd pulse length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
nrd pulse length * t
ncs rd hold length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
11.5
Min
12
0
0
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
-
-
-
-
-
-
1.3
1.3
1.3
1.3
1.3
-
-
-
-
1.4
-
-
2.3
2.3
2.3
2.3
3.6
4
CPSMC
CPSMC
1/(t
Max
AT32UC3A
-
-
cpcpu
1.3
2.3
(1)
)
Units
MHz
Units
ns
ns
774
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