ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 721
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 721 of 826
- Download datasheet (20Mb)
34. Audio Bitstream DAC (ABDAC)
34.1
34.2
32058J–AVR32–04/11
Features
Description
Rev: 1.0.1.1
•
•
•
•
•
The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average
value proportional to the sample value. Two channels are supported, making the Audio Bit-
stream DAC particularly suitable for stereo audio. Each channel has a pair of complementary
digital outputs, DACn and DACn_N, which can be connected to an external high input imped-
ance amplifier.
The Audio Bitstream DAC is compromised of two 3rd order Sigma Delta D/A converter with an
oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter
(Comb4) before being input to the Sigmal Delta Modulator. In order to compensate for the pass
band frequency response of the interpolation filter and flatten the overall frequency response,
the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total frequency
response of the Equalization FIR filter and the interpolation filter is given in
733. The digital output bitstreams from the Sigma Delta Modulators should be low-pass filtered
to remove high frequency noise inserted by the Modulation process.
The output DACn and DACn_N should be as ideal as possible before filtering, to achieve the
best SNR quality. The output can be connected to a class D amplifier output stage, or it can be
low pass filtered and connected to a high input impedance amplifier. A simple 1st order or higher
low pass filter that filters all the frequencies above 50 kHz should be adequate.
Digital Stereo DAC
Oversampled D/A conversion architecture
Digital bitstream outputs
Parallel interface
Connected to DMA Controller for background transfer without CPU intervention
– Oversampling ratio fixed 128x
– FIR equalization filter
– Digital interpolation filter: Comb4
– 3rd Order Sigma-Delta D/A converters
AT32UC3A
Figure 34-2 on page
721
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