ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 318

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 26-19. FSK Modulator Output
26.7.4
Figure 26-20. Synchronous Mode Character Reception
26.7.4.1
32058J–AVR32–04/11
Uptstream Frequencies
unipolar output
FSK Modulator
default polarity
[F0, F0+offset]
NRZ stream
Synchronous Receiver
Manchester
Receiver Operations
encoded
Output
data
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Sampling
Clock
RXD
Txd
1
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 26-20 on page 318
When a character reception is completed, it is transferred to the Receive Holding Register
(RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while
the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into
RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register
(CR) with the RSTSTA (Reset Status) bit at 1.
Start
D0
D1
0
illustrates a character reception in synchronous mode.
D2
D3
D4
0
D5
D6
D7
Parity Bit
Stop Bit
1
AT32UC3A
318