ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 279

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• CKG: Receive Clock Gating Selection
• CKI: Receive Clock Inversion
0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal out-
put is shifted out on Receive Clock rising edge.
1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-
put is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
• CKO: Receive Clock Output Mode Selection
• CKS: Receive Clock Selection
32058J-AVR32-04/11
0x3-0x7
CKO
CKG
0x0
0x1
0x2
CKS
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Receive Clock Output Mode
None
Continuous Receive Clock
Receive Clock only during data transfers
Reserved
None, continuous clock
Receive Clock enabled only if RX_FRAME_SYNC Low
Receive Clock enabled only if RX_FRAME_SYNC High
Reserved
Selected Receive Clock
Divided Clock
TX_CLOCK Clock signal
RX_CLOCK pin
Reserved
Receive Clock Gating
AT32UC3A
RX_CLOCK pin
Input-only
Output
Output
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