ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 438

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29.3
Figure 29-1. MACB Block Diagram
29.4
29.4.1
29.4.2
32058J–AVR32–04/11
Block Diagram
Product Dependencies
I/O Lines
Power Management
High Speed Bus
Peripheral Bus
Master
Slave
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the MACB pins to their periph-
eral functions.
The MACB clock is generated by the Power Manager. Before using the MACB, the programmer
must ensure that the MACB clock is enabled in the Power Manager.
In the MACB description, Master Clock (MCK) is the clock of the peripheral bus to which the
MACB is connected.
The synchronization module in the MACB requires that the bus clock (hclk) runs on at least the
speed of the macb_tx/rx_clk, which is 25MHz in 100Mbps, and 2.5MHZ in 10Mbps in MII mode
and 50MHz in 100Mbps, and 5MHZ in 10Mbps in RMII mode.
To prevent bus errors the MACB operation must be terminated before entering sleep mode.
RX FIFO
Register Interface
DMA Interface
TX FIFO
Statistics Registers
Control Registers
Address Checker
Ethernet Receive
Ethernet Transmit
MII/RMII
MDIO
AT32UC3A
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