ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 408

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
• Data Bus Width (DBW)
• BAT: Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
1: Byte write access type:
0: Byte select access type:
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal.
Table 27-9.
• WRITE_MODE
1: The write operation is controlled by the NWE signal.
0: The write operation is controlled by the NCS signal.
• READ_MODE:
1: The read operation is controlled by the NRD signal.
32058J–AVR32–04/11
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
cycle is resumed from the point where it was stopped.
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
– Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.
– Read operation is controlled using NCS and NRD.
– Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
– Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
0
0
1
1
0
0
1
1
EXNW_MODE
EXNW_MODE
DBW
0
1
0
1
0
1
0
1
32-bit bus
Reserved
Data Bus Width
8-bit bus
16-bit bus
NWAIT Mode
Disabled
Reserved
Frozen Mode
Ready Mode
AT32UC3A
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