ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 270
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 270 of 826
- Download datasheet (20Mb)
25.7.6
25.7.6.1
25.7.7
32058J-AVR32-04/11
Receive Compare Modes
Data Format
Compare Functions
Figure 25-12. Receive Compare Modes
Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each
new sample the last FSLEN bits received at the FSLEN lower bit of the data contained in the
Compare 0 Register (RC0R). When this start event is selected, the user can program the
Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continu-
ously until Compare 1 occurs. This selection is done with the bit (STOP) in RCMR.
The data framing format of both the transmitter and the receiver are programmable through the
Transmitter Frame Mode Register (TFMR) and the Receiver Frame Mode Register (RFMR). In
either case, the user can independently select:
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TX_DATA pin while not in data transfer operation. This is done respectively by the Frame
Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in TFMR.
• the event that starts the data transfer (START)
• the delay in number of bit periods between the start event and the first data bit (
• the length of the data (DATLEN)
• the number of data to be transferred for each start event (DATNB).
• the length of synchronization transferred for each start event (FSLEN)
• the bit sense: most or lowest significant bit first (MSBF).
RX_CLOCK
RX_DATA
(Input)
CMP0
(4 in This Example)
CMP1
Up to 16 Bits
FSLEN
CMP2
CMP3
Start
STTDLY
Ignored
B0
DATLEN
AT32UC3A
B1
B2
STTDLY
)
270
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