ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 573
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 573 of 826
- Download datasheet (20Mb)
30.8.2.11
Offset:
Register Name:
Access Type:
Reset Value:
• TXINI: Transmitted IN Data Interrupt Flag
For control endpoints:
For isochronous, bulk and interrupt IN endpoints:
This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.
• RXOUTI: Received OUT Data Interrupt Flag
For control endpoints:
32058J–AVR32–04/11
PACKET
SHORT
Set by hardware when the current bank is ready to accept a new IN packet. This triggers an EPXINT interrupt if
TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt and to send the packet.
Set by hardware at the same time as FIFOCON when the current bank is free. This triggers an EPXINT interrupt if
TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt, what has no effect on the end-
point FIFO.
The software then writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If
the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are
updated by hardware in accordance with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
Set by hardware when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPXINT
interrupt if RXOUTE = 1.
31
23
15
ru
–
0
0
7
0
CURRBK
USB Endpoint X Status Register (UESTAX)
ru
STALLEDI/
CRCERRI
30
22
14
ru
0
0
0
6
0
BYCT
ru
OVERFI
29
21
13
ru
0
0
0
5
0
0x0130 + X . 0x04
UESTAX, X in [0..6]
Read-Only
0x00000100
NBUSYBK
ru
NAKINI
28
20
12
ru
0
0
0
4
0
NAKOUTI
BYCT
27
19
11
ru
ru
0
–
–
3
0
UNDERFI
RXSTPI/
CFGOK
26
18
10
ru
ru
0
0
–
2
0
CTRLDIR
RXOUTI
25
17
ru
ru
0
0
9
0
1
0
AT32UC3A
DTSEQ
ru
RWALL
TXINI
24
16
ru
ru
0
0
8
1
0
0
573
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