ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 344
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 344 of 826
- Download datasheet (20Mb)
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-
ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag
ITERATION is asserted.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• OVER: Oversampling Mode
0: 16x Oversampling.
1: 8x Oversampling.
• CLKO: Clock Output Select
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin if USCLKS does not select the external clock CLK.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• MSBF/CPOL: Bit Order or SPI Clock Polarity
MSBF = 0: Least Significant Bit is sent/received first.
MSBF = 1: Most Significant Bit is sent/received first.
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
clock/data relationship between master and slave devices.
• CHMODE: Channel Mode
• NBSTOP: Number of Stop Bits
32058J–AVR32–04/11
0
0
1
1
0
– If USART does not operate in SPI Mode (MODE … 0xE and 0xF):
– If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF):
CHMODE
NBSTOP
0
1
0
1
0
Mode Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input..
Remote Loopback. RXD pin is internally connected to the TXD pin.
Asynchronous (SYNC = 0)
1 stop bit
Synchronous (SYNC = 1)
1 stop bit
AT32UC3A
344
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