ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 385
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 385 of 826
- Download datasheet (20Mb)
27.6.5.2
32058J–AVR32–04/11
Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
• An early read wait state is automatically inserted if at least one of the following conditions is
• if the write controlling signal has no hold time and the read controlling signal has no setup time
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0),
Figure 27-18. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
valid:
(Figure
and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode
The write operation must end with a NCS rising edge. Without an Early Read Wait State, the
write operation could not complete properly.
the feedback of the write control signal is used to control address, data, chip select and byte
select lines. If the external write control signal is not inactivated as expected due to load
capacitances, an Early Read Wait State is inserted and address, data and control signals are
maintained one more cycle. See
NBS0, NBS1,
A0, A1
27-18).
CLK_SMC
A[25:2]
D[15:0]
NWE
NRD
Write cycle
Figure
No hold
27-20.
Early Read
Wait state
No setup
Read cycle
AT32UC3A
(Figure
27-19).
385
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