ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 583
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 583 of 826
- Download datasheet (20Mb)
• OVERFE: Overflow Interrupt Enable
Set by software (by setting the OVERFES bit) to enable the Overflow interrupt (OVERFI).
Clear by software (by setting the OVERFEC bit) to disable the Overflow interrupt (OVERFI).
• STALLEDE: STALLed Interrupt Enable
Set by software (by setting the STALLEDES bit) to enable the STALLed interrupt (STALLEDI).
Clear by software (by setting the STALLEDEC bit) to disable the STALLed interrupt (STALLEDI).
• CRCERRE: CRC Error Interrupt Enable
Set by software (by setting the CRCERRES bit) to enable the CRC Error interrupt (CRCERRI).
Clear by software (by setting the CRCERREC bit) to disable the CRC Error interrupt (CRCERRI).
• SHORTPACKETE: Short Packet Interrupt Enable
Set by software (by setting the SHORTPACKETES bit) to enable the Short Packet interrupt (SHORTPACKET).
Clear by software (by setting the SHORTPACKETEC bit) to disable the Short Packet interrupt (SHORTPACKET).
• NBUSYBKE: Number of Busy Banks Interrupt Enable
Set by software (by setting the NBUSYBKES bit) to enable the Number of Busy Banks interrupt (NBUSYBK).
Clear by software (by setting the NBUSYBKEC bit) to disable the Number of Busy Banks interrupt (NBUSYBK).
• KILLBK: Kill IN Bank
Set by software (by setting the KILLBKS bit) to kill the last written bank.
Cleared by hardware when the bank is killed.
Caution: The bank is really cleared when the “kill packet” procedure is accepted by the USB macro core. This bit is auto-
matically cleared after the end of the procedure:
The software shall wait for this bit to be cleared before trying to kill another packet.
Note that this kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent
on the USB line. If at least 2 banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming.
Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
• FIFOCON: FIFO Control
For control endpoints:
For IN endpoints:
For OUT endpoints:
32058J–AVR32–04/11
– The bank is really cleared or the bank is sent (IN transfer): NBUSYBK is decremented.
– The bank is not cleared but sent (IN transfer): NBUSYBK is decremented.
– The bank is not cleared because it was empty.
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints.
When read, their value is always 0.
Set by hardware when the current bank is free, at the same time as TXINI.
Clear by software (by setting the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
Set by hardware when the current bank is full, at the same time as RXOUTI.
AT32UC3A
583
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