ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 440
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 440 of 826
- Download datasheet (20Mb)
29.5.1.2
Table 29-1.
32058J–AVR32–04/11
Bit
31:2
31
30
29
28
27
26
25
24
23
22
21
1
0
Address of beginning of buffer
Wrap - marks last descriptor in receive buffer descriptor list.
Ownership - needs to be zero for the MACB to write data to the receive buffer. The MACB sets this to one once it has
successfully written a frame to memory.
Software has to clear this bit before the buffer can be used again.
Global all ones broadcast address detected
Multicast hash match
Unicast hash match
External address match
Reserved for future use
Specific address register 1 match
Specific address register 2 match
Specific address register 3 match
Specific address register 4 match
Type ID match
VLAN tag detected (i.e., type id of 0x8100)
Receive Buffers
Receive Buffer Descriptor Entry
Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive
three words (12 bytes) of data.
At 100 Mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. In addition, six master clock
cycles should be allowed for data to be loaded from the bus and to propagate through the
FIFOs. For a 60 MHz master clock this takes 100 ns, making the bus latency requirement 860
ns.
Received frames, optionally including CRC/FCS, are written to receive buffers stored in mem-
ory. Each receive buffer is 128 bytes long. The start location for each receive buffer is stored in
memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue
pointer register. The receive buffer start location is a word address. For the first buffer of a
frame, the start location can be offset by up to three bytes depending on the value written to bits
14 and 15 of the network configuration register. If the start location of the buffer is offset the
available length of the first buffer of a frame is reduced by the corresponding number of bytes.
Each list entry consists of two words, the first being the address of the receive buffer and the
second being the receive status. If the length of a receive frame exceeds the buffer length, the
status word for the used buffer is written with zeroes except for the “start of frame” bit and the
offset bits, if appropriate. Bit zero of the address field is written to one to show the buffer has
been used. The receive buffer manager then reads the location of the next receive buffer and
fills that with receive frame data. The final buffer descriptor status word contains the complete
frame status. Refer to
Table 29-1
Word 0
Word 1
for details of the receive buffer descriptor list.
Function
AT32UC3A
440
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