ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 618
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 618 of 826
- Download datasheet (20Mb)
• OVERFI: Overflow Interrupt Flag
Set by hardware when the current Pipe has received more data than the maximum length of the current Pipe. An interrupt
is triggered if the OVERFIE bit is set. Shall be cleared by software (by setting the OVERFIC bit).
• RXSTALLDI: Received STALLed Interrupt Flag
For all endpoints but isochronous. Set by hardware when a STALL handshake has been received on the current bank of
the Pipe. The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set. Shall be cleared to hand-
shake the interrupt (by setting the RXSTALLDIC bit).
• CRCERRI: CRC Error Interrupt Flag
For isochronous endpoint, set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an inter-
rupt if the TXSTPE bit is set. Shall be cleared to handshake the interrupt (by setting the CRCERRIC bit).
• SHORTPACKETI: Short Packet Interrupt Flag
Set by hardware when a short packet is received by the host controller (packet length inferior to the PSIZE programmed
field). Shall be cleared to handshake the interrupt (by setting the SHORTPACKETIC bit).
• DTSEQ: Data Toggle Sequence
Set by hardware to indicate the data PID of the current bank.
For OUT pipe, this field indicates the data toggle of the next packet that will be sent.
For IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
• NBUSYBK: Number of Busy Banks
Set by hardware to indicate the number of busy bank.
For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are busy,
this triggers an PXINT interrupt if UPCONX.NBUSYBKE = 1.
For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this
triggers an PXINT interrupt if UPCONX.NBUSYBKE = 1..
32058J–AVR32–04/11
0
0
1
1
0
0
1
1
NBUSYBK
DTSEQ
0
1
0
1
0
1
0
1
Data toggle sequence
Data0
Data1
reserved
reserved
Number of busy bank
All banks are free.
1 busy bank
2 busy banks
reserved
AT32UC3A
618
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