ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 756
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 756 of 826
- Download datasheet (20Mb)
36.9.7
32058J–AVR32–04/11
CANCEL_ACCESS
For write operations, 32 data bits must be provided, or the result will be undefined. For read
operations, shifting may be terminated once the required number of bits have been acquired.
Table 36-10. MEMORY_BLOCK_ACCESS details
The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% trans-
fer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency.
If a very slow memory location is accessed during a SAB memory access, it could take a very
long time until the busy bit is cleared, and the SAB becomes ready for the next operation. The
CANCEL_ACCESS instruction provides a possibility to abort an ongoing transfer and report a
timeout to the user.
When the CANCEL_ACCESS instruction is selected, the current access will be terminated as
soon as possible. There are no guarantees about how long this will take, as the hardware may
not always be able to cancel the access immediately. The SAB is ready to respond to a new
command when the busy bit clears.
Table 36-11. CANCEL_ACCESS details
Instructions
IR input value
IR output value
DR Size
DR input value (Data read phase)
DR input value (Data write phase)
DR output value (Data read phase)
DR output value (Data write phase)
Instructions
IR input value
IR output value
DR Size
DR input value
DR output value
1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the
2. Apply MEMORY_BLOCK_ACCESS in the IR Scan path.
3. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corre-
4. For a read operation, scan out the contents of the next addressed location. For a write
5. Go to Update-DR.
6. If the block access is not complete, return to Select-DR Scan and repeat the access.
7. If the block access is complete, return to Run-Test/Idle.
first location.
sponding to the next byte, halfword, or word location).
operation, scan in the new contents of the next addressed location.
Details
10010 (0x12)
peb01
34 bits
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
dddddddd dddddddd dddddddd dddddddd xx
eb dddddddd dddddddd dddddddd dddddddd
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Details
10011 (0x13)
peb01
1
x
0
AT32UC3A
756
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