ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 574

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For isochronous, bulk and interrupt OUT endpoints:
This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
• RXSTPI: Received SETUP Interrupt Flag
For control endpoints, set by hardware to signal that the current bank contains a new valid SETUP packet. This triggers an
EPXINT interrupt if RXSTPE = 1.
Shall be cleared by software (by setting the RXSTPIC bit) to acknowledge the interrupt and to free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT
endpoints.
• UNDERFI: Underflow Interrupt Flag
For isochronous IN/OUT endpoints, set by hardware when an underflow error occurs. This triggers an EPXINT interrupt if
UNDERFE = 1.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then auto-
matically sent by the USB controller.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU
is not fast enough. The packet is lost.
Shall be cleared by software (by setting the UNDERFIC bit) to acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
• NAKOUTI: NAKed OUT Interrupt Flag
Set by hardware when a NAK handshake has been sent in response to an OUT request from the host. This triggers an
EPXINT interrupt if NAKOUTE = 1.
Shall be cleared by software (by setting the NAKOUTIC bit) to acknowledge the interrupt.
• NAKINI: NAKed IN Interrupt Flag
Set by hardware when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPX-
INT interrupt if NAKINE = 1.
Shall be cleared by software (by setting the NAKINIC bit) to acknowledge the interrupt.
• OVERFI: Overflow Interrupt Flag
Set by hardware when an overflow error occurs. This triggers an EPXINT interrupt if OVERFE = 1.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for
the packet. The packet is acknowledged and the Received OUT Data interrupt (RXOUTI) is raised as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
32058J–AVR32–04/11
Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt and to free the bank.
Set by hardware at the same time as FIFOCON when the current bank is full. This triggers an EPXINT interrupt if
RXOUTE = 1.
Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt, what has no effect on the
endpoint FIFO.
The software then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is com-
posed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are updated by
hardware in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
AT32UC3A
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